The present invention relates to the field of Universal Asynchronous Receiver/Transmitters (UARTs), and more particularly to a circuit that solves a problem with an oscillating bit in the Line Status Register of the PC16550D during polling operations.
A Universal Asynchronous Receiver/Transmitter (UART) is an interface chip that, in one mode, receives an eight-bit byte of data from an I/O bus at high speed, then, at a much slower speed, transmits a start bit, the eight bits of data, and a stop bit to an external interface. In another mode, the UART receives a start bit, eight bits of data, and a stop bit one bit at a time over a serial interface until the entire data byte is assembled and the processor can then read the data byte from the chip.
All serial devices, such as serial modems, typically use a UART interface chip to communicate with a PC. External modems connect to a PC using a serial cable hooked to one of the PC""s UART-based serial ports, while internal modems have a UART-based serial port on-board.
The UART standard is based on the National Semiconductor model NS16450 UART, which has a single character buffer. An improved version of the 16450 is the National Semiconductor model PC16550D UART, as described in datasheet xe2x80x9cPC16550D Universal Asynchronous Receiver/Transmitter with FIFOs,xe2x80x9d June 1995, which is hereby incorporated by reference. The 16550 has a 16 byte FIFO receive/transmit buffer to reduce buffer overrun errors. Virtually all newer systems use 16550 or compatible UARTs.
The PC16550D provides two ways for the CPU to determine if a full character has been received from the serial interface. The first method uses an interrupt signal asserted on an external pin to alert the processor that a full character has been received. The processor then reads the character from the Receiver Buffer Register, which action resets the interrupt.
In the second method, the processor polls the Data Ready (DR) bit of the 16550 Line Status Register (LSR). When a full character has been read into the Receiver Buffer Register, the UART asserts the DR bit. On a subsequent poll, the processor reads the asserted DR bit and then reads the data byte, which action resets the DR bit. Due to its asynchronous nature, a processor poll of the DR bit may be initiated independent of where the UART is in a data byte read operation.
A problem was discovered with the PC16550D when using the polling mode of operation in 16450 mode wherein the DR bit, as asserted on the UART data bus during a LSR read operation, is observed to rapidly oscillate during the valid data interval. The underlying cause of the oscillation is unknown, however it is repeatable. Observation shows that the oscillation occurs when a read strobe signal is asserted to the UART at or right after a data byte read has completed. When signal RD is asserted approximately 15 nsec before signal RXRDY (active low) is asserted by the UART, the rapid oscillation is observed. In a test configuration where the read strobe is allowed to remain asserted, the oscillation was observed to continue for more than 4 microseconds. When the read strobe is deasserted, the oscillation ceases, and in particular does not continue beyond the read to floating delay interval.
Since the DR bit oscillation only occurs after a data byte read has completed, a poll of the DR bit will not indicate a false positive, but may indicate a false negative.
One problem that the oscillating DR bit can cause is a data bus parity error at the processor. When the data bus and the output of the parity checking circuit of the processor are latched into a register, the parity may not be in synchronization with the data bus values, leading to data bus parity error indications.
Another problem that the oscillating DR bit can cause is a system fault in systems having micro-synchronized microprocessors. If the two micro-synchronized microprocessors do not read the LSR register value from the UART data bus at exactly the same time, the oscillation may cause one of the microprocessors to read a different value of the oscillating DR bit than the other microprocessor, which will cause a system fault.
Accordingly, it is an object of the present invention to provide a circuit for use in conjunction with a PC16550D UART in 16450 polling mode that will filter out the DR bit oscillations and eliminate parity and micro-synchronization errors.
The invention of Applicant latches the value of the LSR during the valid data portion of a LSR register read cycle, then deasserts the read strobe, delays a sufficient time to allow the data bus values to float, and hence delays a sufficient time to allow the DR bit oscillations to end, applies the latched values of the LSR to the data bus, then asserts a ready signal to the microprocessor. If the UART access is not a read cycle to the LSR, the delay time to allow the data bus values to float is bypassed, and the UART access cycle proceeds normally.